发明名称 SEMICONDUCTOR MEMORY DEVICE AND MEMORY METHOD THEREOF
摘要 PURPOSE: A semiconductor memory device is provided to prevent the increase of time requiring for write verification and to repress the increase of area occupied by a latch circuit in a chip. CONSTITUTION: A memorizing method of a memory device is composed of the following steps. First or second logic level data are memorized in data memory circuits(310-312111). If the first logic level data are stored in the data memory circuits, the state of memory cells(M1-M16) is set as i. If the second logic level data are stored, the state of memory cells is maintained. If the memory cell reaches the i state while being within 1-i, the data in the data memory circuits are changed into a second logic level. If the memory cell does not reach the i state while being within 1-i, the first logic level of data is maintained. If the memory cell is in a range of i+1-n, the data in the data memory circuits are maintained. When the memory cell is transit from i-1 to i, the memory cell is controlled. Thus, the memory cell is prevented from being changed from i+1 to n. Therefore, the area occupied by a latch circuit in a chip and time for write verification is prevented from increasing.
申请公布号 KR20000048392(A) 申请公布日期 2000.07.25
申请号 KR19990061665 申请日期 1999.12.24
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 SHIBATA NOBORU;TANAKA TOMOHARU
分类号 G11C16/02;G11C7/00;G11C11/56;G11C16/04;H01L21/8247;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):G11C7/00 主分类号 G11C16/02
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