发明名称 METHOD FOR TESTING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE
摘要 PURPOSE: A method for testing a semiconductor memory device is provided to perform by synchronously adopting an outer command and an outer address with a clock signal of high frequency at the same time CONSTITUTION: To test a semiconductor memory device, capacitors(C1-C4) are accessed in a signal line by conducting switching circuits(SW1-SW4). A control signal is offered to the signal line and a transmitting time of control signal is measured. A capacitance of signal line is changed by changing a number of conductive switching circuits(SW1-SW4). A semiconductor memory device adopted an outer command and an outer address by synchronizing a clock signal contains the signal line, plural capacitors(C1-C4), a setting circuit of test mode(13) and a selecting circuit(12).
申请公布号 KR20000047496(A) 申请公布日期 2000.07.25
申请号 KR19990040659 申请日期 1999.09.21
申请人 FUJITSU LIMITIED 发明人 NINOMIYA KAZUHIRO;HIJIOKA SHINYA;SATO YASUHIRU
分类号 G11C11/407;G01R31/28;G11C11/401;G11C11/406;G11C29/00;G11C29/06;G11C29/12;(IPC1-7):G11C29/00 主分类号 G11C11/407
代理机构 代理人
主权项
地址