| 摘要 |
PURPOSE: A test logic circuit is provided to process at high speed and to automatically verify a miss-operation of memory. CONSTITUTION: To test a memory cell(21), a test pattern is written in a register inside a control unit of write data pattern(26). An initial address to be tested is written in an address storage unit inside a generating unit of write address. A number to test is written in an address counter unit, and then a test mode is set. The write data is fed to a write data port(22) and transferred to the memory cell(21). A generating unit of read address(28) generates a read address by supplying the write address when a next write address is supplied. The read address is transferred to a decoder of read address(25). The read data is transferred to a data comparing unit(29) by outputting through a read data port(24). The data comparing unit(29) transfers the data supplied from a patterning unit of test data(26) to a comparator by matching a timing with the read data. The comparator decides a miss-operation of memory cell(21) by comparing the write data and the read data.
|
