| 摘要 |
PURPOSE: A memory error emulator is disclosed to synchronize with the memory's timing signal and artificially generate electronic signals of memory cell and surrounding logic's errors. CONSTITUTION: A memory error emulator is composed of separation, output, latch, comparison, and synchronization. A timing controller(100) separates row and column addresses according to a Row Address Strobe signal(RAS), A column Address Strobe signal(CAS), possible a record signal(/WE), and possible an output signal(/OE), it generates and latches a control signal and an output control signal at the same time. Address latcher(110) selectively latches address that has been inputted through an address line according to latch signals generated by the timing controller. An external interface and the memory controller(120) stores a port cell's address appointed from outside and stores a memory cell's default value. An address comparer(130) compares port cell's row/column address saved under an external interface memory controller's control and row/column address latched by the address latcher and it outputs the resulting values(/CP). An output controller (140) synchronizes the output control signal of the timing controller to address comparer's output address comparison value and outputs saved memory cell's default value.
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