LOW THRESHOLD MOS TWO PHASE NEGATIVE CHARGE PUMP

摘要

A triple well charge pump comprises a first transistor connected in a diode configuration having a first channel terminal (61), nominally the source, coupled to a first node, and the second channel terminal (62), nominally the drain, coupled to its gate (64) and to a second node (66). A first capacitor (65) has a first terminal coupled to the first node of the charge pump, and a second terminal adapted to receive a first clock signal (CK). A second transistor has a first channel terminal (72) coupled to the second node of the charge pump, and a second channel terminal (73) coupled to its gate (74) and to a third node. A second capacitor (85) has a first terminal coupled to the second node, and second terminal adapted to receive a second clock signal (CKB). The first and second transistors comprise a first region and a second region having a first conductivity type (n+) providing the first and second channel terminals respectively, a channel region (57) in which the first and second regions are formed having a second conductivity type, and an isolation well (51) having the first conductivity type in a semiconductor substrate (50). The first and second regions, the channel region and the isolation well form a parasitic bipolar junction transistor that has a threshold voltage. The channel region has a doping concentration establishing a threshold voltage for the MOS transistor which is less than the threshold voltage of the parasitic bipolar junction transistor. The clock signals have sloped rising and falling edges.