A dram capable of selectively performing a self-refresh operation

摘要

A dynamic random access memory (DRAM) includes a plurality of row decoders (203) for selecting word lines of the memory cells of the memory banks (201), an address generator (209) for generating internal addresses (FRA) which sequentially vary during a self-refresh mode, a refresh bank designating circuit (207) for generating refresh bank designating signals (PRFH) for designating a memory bank (201) to be refreshed, and a bank selection decoder (213) for designating one or more memory banks (201) to be refreshed by the refresh bank designating signals (PREF) and supplying refresh addresses (DRA) to the row decoders (203) corresponding to the designated memory banks (201) according to the information of the internal addresses. The self-refresh operation is performed only with respect to selected memory banks or memory banks in which data is stored, thereby minimizing power consumption.