| 摘要 |
<p>A phase-locked loop circuit is provided with an oscillator (5) which outputs a pulse signal, and a frequency divider (1) for frequency-dividing the pulse signal. The frequency divider (1) is provided with a dividing factor switching circuit (11, 12, 13, 14) which switches the dividing factor before a phase of the pulse signal is locked to that of a reference clock signal. <IMAGE></p> |
