Stacked capacitor DRAM cell

摘要

A DRAM cell is provided that has a reduced area while maintaining capacitance. The MOSFET is conventionally formed in and on a semiconductor substrate and the storage capacitor (e.g., 205a, 205b) for different DRAM cells are formed in different layers (e.g., 210, 240) of an integrated circuit. As a result, the storage capacitors may be overlapped reducing cell size.