| 摘要 |
<p>A system and method for buffering data entries using a memory and one or more registers, where control logic controls the operations of the memory and the registers. The memory provides for relatively deep and wide storage of data entries, while the registers ensure that a data entry may be written in and/or read out on each clock cycle. A buffer configured to store a plurality of data entries comprises a memory, one or more registers coupled between an output of the memory and an output of the buffer, and control logic coupled to the registers and to the memory. The memory and the registers each store data entries in data entry storage locations. The combination of memory with the registers coupled between an output of the memory and an output of the buffer may advantageously result in a small footprint and low power consumption. The speed of the registers is added to the high depth and width to size ratio of the memory. The number of registers in the buffer is determined by the number of clock cycles of read latency of the memory or by the number of clock cycles between the clock cycle when a data entry is requested from the memory and the clock cycle when the data entry is available to be read from the memory. The number of registers may be set to optimize the speed gain from the use of registers, while minimizing the size and power consumption to depth and width ratio. <IMAGE></p> |
