| 摘要 |
A method of forming a capacitor for a stacked DRAM memory cell. A contact hole is formed in a dielectric stack of an interlayer dielectric, a first nitride layer, a high temperature oxide (HTO) layer, and a second nitride layer. An in-situ doped amorphous silicon segment is formed in and over the contact hole. The second nitride layer is removed and then a hemispherical grain (HSG) polysilicon layer is formed over the amorphous silicon segment. The HTO layer is removed and a capacitor dielectric layer is formed over the HSG polysilicon layer. Finally, a top conductive layer is formed over the capacitor dielectric layer.
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