| 摘要 |
PROBLEM TO BE SOLVED: To enhance reliability of a semiconductor memory by arranging the gate of transistors constituting a peripheral circuit at a constant interval using a dummy gate thereby minimizing fluctuation of process deviation, i.e. suppressing fluctuation in the threshold voltage of the transistor. SOLUTION: The source of a transistor is arranged while being divided into three and the drain is arranged while being divided into two. L represents the length of the gate and the dummy gates DG1, DG2, DG3, DG4, DG5, DG6 of transistors P1, P2, P3, P4, N1, N2, N3. W2/2 represents the width of gate of PMOS transistors P1, P2, P3 and the NMOS transistors N3, N4, W1/2 represents the width of gate of NMOS transistors N1, N2, W3 represents the width of the dummy gates DG5, DG6, W4, W5 represent the width of the dummy gates DG1, DG4, and W4 represents the width of the dummy gates DG2, DG3. In this embodiment, the gates are arranged at a constant interval (a) in order to suppress fluctuation of process deviation. |
