发明名称 |
Semiconductor memory device with improved test efficiency |
摘要 |
I/O lines in an I/O gate-sense amplifier portion are arranged in the order of IOA, /IOB, IOB, and /IOA. As a result, the potentials of adjacent I/O lines are necessarily different at the time of writing/reading the same data to/from a plurality of memory cells during a multi-bit test. Therefore, a short-circuit fault caused between adjacent I/O lines can be detected at the same time.
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申请公布号 |
US6091651(A) |
申请公布日期 |
2000.07.18 |
申请号 |
US19980165502 |
申请日期 |
1998.10.02 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
FURUTANI, KIYOHIRO;HAMAMOTO, TAKESHI;KIKUDA, SHIGERU |
分类号 |
G01R31/28;G11C29/02;G11C29/34;G11C29/50;H01L21/8242;H01L27/108;(IPC1-7):G11C7/00 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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