Method and system for using voltage and temperature adders to account for variations in operating conditions during timing simulation

摘要

A method and system for predicting the sensitivity of the integrated circuit logic cell timing performance to variations in voltage and temperature. Rather than using the prior art approach of multiplicative derating factors to model voltage and temperature effects on timing performance, adders are used to model the change in performance due to variations in operating conditions (i.e., voltage and temperature). The adders are treated as functions of input transition time (Tx) and output load capacitance (Cload). The change in performance as measured in time forms a plane over the Tx-Cload operating range for variations in either voltage or temperature. The adders, using a plane equation as a function of Tx and Cload, greatly improve the absolute accuracy in predicting the effects of variations in voltage and temperature, as compared to using the prior art methods involving multiplicative derating factors.