Process for fabricating a semiconductor structure having a self-aligned spacer

摘要

A self-aligned dielectric spacer is etched by providing capped gate structure along a second layer of dielectric material located above the gate cap material. Dopant material at an increased doping level is provided in the second layer of dielectric material where the self-aligned spacer is to be located. The second layer of dielectric material is then etched selective to the dopant to define the self-aligned dielectric spacer.