发明名称 MULTIPLYING AND DIVIDING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a multiplying and dividing circuit which can be constituted only of a device in a CMOS process. SOLUTION: This circuit is provided with current/voltage converting circuits 124, 125, and 126 constituted of PNP transistors and buffer amplifiers for logarithm compressing first, second, and third input signals, and a first differential amplifier circuit 127 for performing the arithmetic operation of the logarithm- compressed first and second input signals, and a second differential amplifier circuit 128 for performing the arithmetic operation of the output of the first differential amplifier circuit and the logarithm-compressed third input signal, and a voltage/current converting circuit 129 constituted of arithmetic amplifier circuits and PNP transistors and NMOS transistors for inverse logarithm extending the output of the second differential amplifier circuit. The collector, base, and emitter of the PNP transistor are respectively formed of a P type silicon substrate, N well, and P diffused layer so that a multiplying and dividing circuit can be constituted.
申请公布号 JP2000201033(A) 申请公布日期 2000.07.18
申请号 JP19990001946 申请日期 1999.01.07
申请人 OLYMPUS OPTICAL CO LTD 发明人 HIRAIDE SHUZO
分类号 H01L27/06;H01L21/8249;H03F3/347;(IPC1-7):H03F3/347;H01L21/824 主分类号 H01L27/06
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