发明名称 |
Merged VLSI implementation of hardware optimized Q-Coder and software optimized QM-Coder |
摘要 |
The present invention includes a method and circuit for the compression encoding and decoding of digital images. In particular, the method is directed to an improved implementation of the QM-Coder as defined in the JBIG Standard and a merged implementation of the QM-Coder as defined in the JBIG Standard with the Q-Coder as defined by the IBM ABIC standard. The improved implementation of the QM-Coder as defined in the JBIG Standard includes an improved CLEARBITS procedure. The merged implementation of the QM-Coder as defined in the JBIG Standard and Q-Coder as defined by the ABIC standard includes the sharing of hardware to reduce implementation logic.
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申请公布号 |
US6091854(A) |
申请公布日期 |
2000.07.18 |
申请号 |
US19980137246 |
申请日期 |
1998.08.20 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
SLATTERY, MICHAEL JOHN;MITCHELL, JOAN LAVERNE |
分类号 |
H03M7/40;H04N1/417;(IPC1-7):G06K9/36 |
主分类号 |
H03M7/40 |
代理机构 |
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地址 |
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