发明名称 CHIP SIZE SEMICONDUCTOR PACKAGE, AGGREGATE THEREOF AND MANUFACTURE THEREOF
摘要 PROBLEM TO BE SOLVED: To provide a chip size semiconductor package which is simple in structure, equipped with extraction terminals enhanced in number, lessened in thickness, formed as small in size as a chip, and reduced in cost by simplification of a manufacturing process. SOLUTION: This package is composed of a semiconductor chip 10, wires 50 whose one ends are each bonded to the pads 12 of the semiconductor chip 10, a sealing material 60 which seals up the wires 50 and the top surface the semiconductor chip 10, and extraction terminals 70 which are each formed on the other ends of the wires 50. A manufacturing method comprises a first step where adjacent semiconductor chips are connected together with wires on a wafer 80, a second step where the semiconductor chips and the wires are sealed up with a sealing material, a third cutting step where the semiconductor chips are divided into separate chips, and a fourth step where the extraction terminals are each formed on the other ends of the wires which are exposed on the outside of the sealing material.
申请公布号 JP2000200859(A) 申请公布日期 2000.07.18
申请号 JP19990341120 申请日期 1999.11.30
申请人 ANAM SEMICONDUCTOR INC 发明人 TEI CHIEI
分类号 H01L23/12;H01L21/56;H01L23/31;H01L23/498;H01L23/528 主分类号 H01L23/12
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