Using ECC/parity bits to store predecode information

摘要

A microprocessor configured to store predecode information that is removed from an instruction cache is disclosed. In one embodiment, the microprocessor comprises a predecode unit and an instruction cache. The predecode unit is configured to receive instruction bytes from a level two cache and generate corresponding predecode information. The instruction cache is coupled to the predecode unit and comprises two pluralities of storage locations, one for storing instruction bytes and a second for storing predecode information corresponding to the instruction bytes. The instruction cache is configured to receive and store the instruction bytes and predecode information from the predecode unit. The instruction cache is also configured to output at least part of the corresponding predecode information for storage in the level two cache when the instruction bytes and corresponding predecode information are replaced in the instruction cache. The predecode information may be stored in storage locations within the level two cache that are configured to store parity and or error checking and correction information. A method for storing predecode information in a level two cache when it has been overwritten in an instruction cache is also disclosed. A computer system configured to store predecode information in a level two cache is also disclosed.