发明名称 Semiconductor memory
摘要 A plurality of information memory cells and a single reference memory cell are coupled to a single word line. The reference memory cell stores reference information equivalent to a reference potential to information readout. Pieces of information, stored in the information memory cells, are fed, over respective bit lines, to first input terminals of sense amplifiers. The reference information, stored in the reference memory cell, is fed, over a bit line, to second input terminals of the sense amplifiers. When the potential of signal charges stored in the information memory cells falls due to leakage current, the potential of a signal charge stored in the reference memory cell correspondingly falls due to leakage current. This prolongs a length of time taken for a difference between these potentials to reach a sense limit, thereby achieving a longer data retention time. As a result of such arrangement, even when there occurs a small current leakage from memory cells, it is possible to secure a long data retention time thereby making it possible to obtain a long refresh cycle period.
申请公布号 US6091655(A) 申请公布日期 2000.07.18
申请号 US19970972444 申请日期 1997.11.18
申请人 MATSUSHITA ELECTRONICS CORPORATION 发明人 YAMADA, TOSHIO;SHIBAYAMA, AKINORI
分类号 G11C11/409;G11C7/06;G11C7/14;G11C11/401;G11C11/406;G11C11/4091;G11C11/4099;G11C29/00;G11C29/04;H01L21/8242;H01L21/8246;H01L27/10;H01L27/105;H01L27/108;(IPC1-7):G11C7/02 主分类号 G11C11/409
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