| 摘要 |
PURPOSE: A digital phase locked loop circuit is provided to prevent a cycle slip appearance by limiting a phase error, which is generated when an error of a phase and a frequency is in a predetermined range, with a predetermined value. CONSTITUTION: A digital phase locked loop circuit comprises a multiplication part(21) which multiplies input data(Din) and an output of a voltage controlled oscillator(22). A phase detector(26) detects a phase of output data of the multiplication part(21). A limiter(25) limits an output of the phase detector(26) by a predetermined phase error value. A synchronous detector(27) detects whether an error of a phase and a frequency of output data of the multiplication part(21) exists in a predetermined range, and outputs a 'LOCK' signal when the error exists in the predetermined range. A multiplexer(24) selectively outputs output signals of the phase detector(26) and the limiter(25) according to an output of the synchronous detector(27). A loop filter(23) determines an oscillation frequency according to an output of the multiplexer(24), and the voltage controlled oscillator(22) outputs the signal having a constant oscillation frequency according to an output of the loop filter(23).
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