| 摘要 |
PURPOSE: A phase locked loop(PLL) circuit is provided to prevent a jitter by reducing a difference of charge and discharge currents. CONSTITUTION: A phase locked loop(PLL) circuit comprises a charge pump circuit which consists of a first overlap clock generating part(700), a second overlap clock generating part(800) and a charge pump part(900). The charge pump circuit(100) receives a first control signal(UP) from a phase detector in order to control a charge operation of the charge pump circuit, and a second control signal(DN) therefrom in order to control a discharge operation of the charge pump circuit. The first overlap clock generating part(700) generates a pair of first clock signals in response to the first control signal(UP). The logic low levels of the first clock signals(A,B) are overlapped. The second overlap clock generating part(800) generates a pair of second clock signals in response to the second control signal(DN). The logic high levels of the second clock signals(C,D) are overlapped. The charge pump part(900) charges and discharges an output terminal(LF) in response to the first and second clock signals(A,B,C,D).
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