发明名称 |
ERROR CORRECTION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE |
摘要 |
An error correction/detection circuit including a syndrome generating circuit for generating a syndrome from information data and check data input in a first cycle; and an error position/size calculating circuit for calculating a position and a size of an error from said syndrome; and an error correction circuit for correcting an error for at least information data input in a second cycle on a basis of the position and the size of the error obtained in said error position/size calculating circuit and for outputting at least error-corrected information data.
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申请公布号 |
KR100261790(B1) |
申请公布日期 |
2000.07.15 |
申请号 |
KR19960006776 |
申请日期 |
1996.03.14 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
TANZAWA, TORU;TANAKA, TOMOHARU;SHIROTA, RIICHIRO;OHUCHI, KAZUNORI |
分类号 |
G06F12/16;G06F11/10;H03M13/15;(IPC1-7):G06F11/10 |
主分类号 |
G06F12/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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