| 摘要 |
PURPOSE: A chip size package and a fabrication method thereof are provided to simplify a fabrication process and reduce a fabrication time, and thereby to reduce a fabrication cost. CONSTITUTION: To fabricate a chip size package, a wafer including chips(10) and a pattern tape(20) are first provided. While each chip(10) has pads(11) peripherally formed thereon, the tape(20) has lands(21) corresponding to the pads(11) and metal layers(22) centrally formed thereon as under bump metallurgy. The lands(21) and the metal layers(22) are respectively connected by metal patterns(23). Second, the tape(20) is attached on the chip(10) by an adhesive(70), and then the pads(11) and the lands(21) are connected by metal wires(30). Third, as the wafer is cut along scribe lines, the chips(10) are individually separated. On the other hand, a base frame having ball lands(41) corresponding to the pads(11) and solder bumps(42) formed on the ball lands(41) is provided. The base frame is attached to the chip(10) by connection between the bumps(42) and the metal layers(22). Next, the chip(10) is molded by an encapsulant(50) and then separated from the base frame. Finally, solder balls(60) are formed on the ball lands(41).
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