| 摘要 |
PURPOSE: An euclid calculating circuit is provided to be capable of being operated by a single clock and to have a less circuit area and a low consumption power. CONSTITUTION: A Euclid calculating circuit comprises first and second address generating parts(27,31) each of which generates an address. A first plus-one adder(28) adds an integer '1' to the address of the first address generating part(27), and a second plus-one adder(32) adds an integer '1' to the address of the second address generating part(31). A first memory(21) has two memory regions(Ra,Ra'), and a second memory(22) has two memory regions(Rb,Rb'). Each of first and second multiplexers(29,30) receives the addresses from the first address generating part(27) and the plus-one adder(28), and transfers either one of the received addresses to the memory regions(Ra,Rb) of the first and second memories(21,22) in response to a state signal(state). Each of third and fourth multiplexers(34,35) receives the addresses from the second address generating part(31) and the plus-one adder(32), and transfers either one of the received addresses to the memory regions(Ra',Rb') of the first and second memories(21,22) in response to the state signal(state). Upper and lower control calculation parts(23,24) control the memories(21,22), and calculate inputted data, respectively.
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