| 摘要 |
PURPOSE: An up-down counter is provided to perform a count operation without using a complex carry-look ahead circuit. CONSTITUTION: An up-down counter comprises first to fourth multiplexers(32a,32b,32c,32d) and first to fourth D flip flops(31a,31b,31c,31d). Each of the multiplexers(32a,32b,32c,32d) receives an up/down signal(up/down) for determining an up counter or a down counter. The first to fourth multiplexers(32a,32b,32c,32d) are disposed at previous stages of the first to fourth D flip flops(31a,31b,31c,31d) so as to correspond, respectively. The first multiplexer(32a) receives an output value(X3) of the fourth D flip flop(31d) and a combined value, which is obtained by exclusive ORing an input value(X1) and the output value(X3), and outputs either one of the received values in response to the up/down signal(up/down). The second multiplexer(32b) receives output values(X0,X2) of the first and third D flip flops(31a,31c) to output either one of the received values in response to the up/down signal(up/down). The third multiplexer(32c) receives output values(X1,X3) of the second and fourth D flip flops(31b,31d) to output either one of the received values in response to the up/down signal(up/down). The fourth multiplexer(32d) receives an output value(X2) of the D flip flop(31c) and a combined value, which is obtained by exclusive ORing the output values(X0,X1), and outputs either one of the received values in response to the up/down signal(up/down).
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