METHOD FOR FABRICATION A SPLIT GATE FLASH EEPROM CELL

摘要

PURPOSE: A self-aligned flash EEPROM cell fabrication method is provided to improve a step-coverage of tungsten silicide and improve an yield by using double self-aligned etching processes. CONSTITUTION: A tunnel oxide(32) and a first polysilicon layer(33) are formed on a semiconductor substrate(31) having a field oxide. An ONO dielectric(34), a second polysilicon layer(35) and a top oxide film(36) are sequentially formed on the resultant structure. By performing a first self-aligned etching the top oxide(36), the second polysilicon layer(35) and the ONO dielectric(34) using a photoresist pattern(61) as a mask, a control gate(35A) is formed. By performing a second self-aligned etching using the patterned top oxide film(36) as a mask, a split gate structure is formed.