发明名称 STACKED CHIP SIZE PACKAGE AND MANUFACTURING METHOD THEREOF
摘要 PURPOSE: A stacked chip size package and a manufacturing method thereof are provided to enable a stack of the same chips having the identical circuitry pattern. CONSTITUTION: An upper and a lower semiconductor chips(12,12') have a plurality of chip pads(12a) formed thereon, respectively, and stud bumps(13) formed on the chip pads(12a). The upper and lower chips(12,12') are attached to front and rear faces of a substrate(11), respectively. At this time, the stud bumps(13) on the chips(12,12') are joined to upper and lower lands(11a) each formed on the front and rear faces of the substrate(11). A liquid polymer(14) is filled between the chips(12,12') and the substrate(11) while embedding the stud bumps(13). In addition, the substrate(11) has a plurality of leads(11b) formed along both opposing ends of the front face and laterally extended. The lead(11b) will be bent into an adequate form for next level mounting. In particular, the substrate(11) has internal circuitry patterns(12b) linking the intersectional upper and lower lands(11a) together. Accordingly, the upper and lower chips(12,12') can be stacked to face each other though the chips(12,12') have the identical circuitry pattern.
申请公布号 KR20000043073(A) 申请公布日期 2000.07.15
申请号 KR19980059380 申请日期 1998.12.28
申请人 HYUNDAI MICRO ELECTRONICS CO., LTD. 发明人 HEO, GI ROK
分类号 H01L23/04;(IPC1-7):H01L23/04 主分类号 H01L23/04
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