| 摘要 |
PURPOSE: A subsidiary word line decoder is provided to elevate yield rate by reducing the number of transistors and by widening a process window. CONSTITUTION: In case of the 'logic low' level of one main word line(MWL0), the 'logic low' level potential is delivered to the other main word line(MWL1) through an NMOS transistor(MN3). Herein, the NMOS transistor is turned on by an inversing signal(/PX+0) of a boosting signal for connecting two subsidiary word lines(SWL0,SWL1). Therefore, two adjacent subsidiary word lines(SWL0,SWL1) are turned off at the same time. Thus, the number of transistors is reduced for reducing the area of chips to improve yield rate.
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