发明名称 CLOCK FREQUENCY CONVERTING APPARATUS OF DIGITAL SIGNAL RECEIVING DEVICE
摘要 PURPOSE: A clock frequency converting apparatus is provided to prevent an omission or a duplication phenomenon in processing a video signal by providing a corresponding clock frequency to a corresponding block. CONSTITUTION: A switching unit(208c) selects one of the clock frequencies outputted from first and second phase locked loops(208a, 208b). A controller(212) controls the switching unit(208c) to output a clock frequency corresponding according to a frame rate of an inputted digital signal. The first phase locked loop(208a) generates a clock frequency of 74.25MHz and the second phase locked loop(208b) generates a clock frequency of 74.175MHz. The controller(212) controls the switching unit(208c) to select one of the clock frequencies from the first and second phase locked loops according to frame rates.
申请公布号 KR20000043102(A) 申请公布日期 2000.07.15
申请号 KR19980059415 申请日期 1998.12.28
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 SON, TAE YONG
分类号 H04N5/44;(IPC1-7):H04N5/44 主分类号 H04N5/44
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