| 摘要 |
PURPOSE: A bi-orthogonal walsh modulator is provided to reduce a calculation amount of a receiver without dropping a system performance. CONSTITUTION: A bi-orthogonal walsh modulator comprises a serial-to-parallel convertor(20) and a 64-array bi-orthogonal walsh modulating part(21). The serial-to-parallel convertor(20) receives a data bit to output a convolutional coded bit sequence(b0,b1,b2,b3,b5). The 64-bit bi-orthogonal walsh modulating part(21) modulates remaining lower bits of the convolutional coded bit sequence(b0,b1,b2,b3,b5) except for a most significant bit(b5) in a bi-orthogonal walsh sequence, and uses a parity bit for determining an inverse part of the 64-bit bi-orthogonal walsh sequence.
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