LATENCY CIRCUIT OF WRITE COMMAND AND CONTROL METHOD THEREOF

摘要

PURPOSE: A latency circuit of write command and a control method thereof are provided to reduce a loading of master clock and power consumption. CONSTITUTION: A latency circuit of write command is equipped with devices as follows. A command decoder(3) outputs by decoding an input of command address. An inner clock generator(5) outputs an inner clock during operating latency by responding to an input of master clock. A register decoder(9) inputs register data and outputs by decoding. A burst control unit(11) outputs a pulse of write command by inputting an output signal of command decoder and the inner clock. A shift register(13) shifts and outputs an output signal of burst control unit by responding to the input of inner clock. An output unit(15) outputs a write signal having a needed delay by inputting an output signal of shift register and register decoder.