发明名称 CLOCK GENERATING APPARATUS
摘要 PURPOSE: A clock generating apparatus is provided to improve an access time by making an internal clock be toggled at a rising edge of an external clock. CONSTITUTION: A clock generating apparatus comprises a frequency storing part(100), a delay selecting part(200), and a delay chain part(300). The frequency storing part(100) has a first fuse(1), a second fuse(11) and a plurality of combination circuits(21,31,41,51). Each of the combination circuits(21,31,41,51) receives state signals of the fuses(1,11) to output a combination signal. One of combination signals from the frequency storing part(100) is activated. The delay chain part(300) consists of a plurality of serially connected unit delays, each of which delays an output of an unit delay at a previous stage. The unit delay of a first stage delays an internal clock signal(CLK_M). The delay selecting part(200) receives delayed clock signals from the delay chain part(300), and outputs either one of the received delayed clock signals in response to the combination signals from the frequency storing part(100).
申请公布号 KR20000045379(A) 申请公布日期 2000.07.15
申请号 KR19980061937 申请日期 1998.12.30
申请人 HYUNDAI ELECTRONICS IND. CO., LTD. 发明人 PARK, JONG HUN
分类号 H03K3/00;(IPC1-7):H03K3/00 主分类号 H03K3/00
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