| 摘要 |
PURPOSE: A fabrication of a model pattern used for a simulation of chemical mechanical polishing(CMP) process of an interlayer dielectric is provided to facilitate a sampling of model parameter and to improve a reliability of measurement. CONSTITUTION: To simulate a chemical mechanical polishing(CMP) process of an interlayer dielectric(33), a model pattern including a polishing stop layer(32) is fabricated. First, an oxide layer(31) is deposited and selectively etched on a silicon wafer(30), and then a silicon nitride layer(32) is deposited thereon. Next, the interlayer dielectric(33) is deposited on the silicon nitride layer(32) and then selectively etched to obtain planarized surfaces. Subsequently, the chemical mechanical polishing process is performed with respect to the interlayer dielectric(33) by using a slurry composition. Then, resultant parameters such as a dishing or an edge polish profile are measured by using a declinometer or an optical thickness measure. In particular, the silicon nitride layer(32) is employed as the polishing stop layer not damaged during the chemical mechanical polishing process.
|
