| 摘要 |
PURPOSE: A power saving device for a processor is provided to reduce power consumption of a full processor by minimizing power loss from an unused unit block, through stopping an operation of the unused unit block in a processor having a pipeline structure. CONSTITUTION: A power saving device for processor comprises a power decoding controller(110), multiplexers(120-1-n), and command executers(130-1-n). The power decoding controller(110) decodes a command, to decide either a power decoding, and to output control signals. The multiplexers(120-1-n) select a system clock by each control signal. The command executers(130-1-n) execute a corresponded command by receiving the system clock from each multiplexers(120-1-n). The power saving device stops an operation of an unused command executer in decoding the power.
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