发明名称 CHIP SIZED STACK PACKAGE
摘要 PURPOSE: A chip sized stack package is provided to realize a simple interconnection scheme between the identical functional pads. CONSTITUTION: An upper and a lower semiconductor chips(30,40) are disposed in the same direction, that is, respective pads(31,41) on the chips(30,40) face downward. In addition, an upper pattern tape(10) is attached to a rear side of the lower chip(40), and the upper chip(30) is disposed above the upper pattern tape(10) through a first interlaid elastomer(32). Moreover, a lower pattern tape(20) having ball lands is attached toward a front side of the lower chip(40) through a second interlaid elastomer(42). While connection pads(22) formed in the lower pattern tape(20) are connected with metal patterns(11) of the upper pattern tape(10), the metal patterns(11) are also connected with the pads(31) of the upper chip(30). Furthermore, metal patterns(21) of the lower pattern tape(20) connect the pads(41) of the lower chip(40) with the ball pads, and the connection pads(22) are connected with the lower metal patterns(21) via bridges(24). Besides, a mold body(50) and solder balls(70) are further formed.
申请公布号 KR20000043573(A) 申请公布日期 2000.07.15
申请号 KR19980059971 申请日期 1998.12.29
申请人 HYUNDAI ELECTRONICS IND. CO., LTD. 发明人 PARK, MYEONG GEUN
分类号 H01L23/522;(IPC1-7):H01L23/522 主分类号 H01L23/522
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