发明名称 FABRICATION METHOD OF CHIP SIZED PACKAGE
摘要 PURPOSE: A method for fabricating a chip sized package is provided to realize a simpler structure and a shorter electrical path than ever and to enhance a solder joint reliability. CONSTITUTION: A semiconductor chip(20) is coated with an insulating layer(60). The insulating layer(60) is then partly etched to expose chip pads(21) formed on the chip(20). Next, metal lines(40) are deposited while extending over the insulating layer(60) from the respective chip pads(21). A circuit tape may be alternatively used instead of the metal lines(40) and the insulating layer(60). On the other hand, a frame coated with a first photoresist layer except ball lands is provided. A copper layer(100) is deposited on overall surfaces of the frame, and a second photoresist layer is then coated on the copper layer(100) except the ball lands. After metal bumps are formed on the ball lands, the second photoresist layer is removed. Next, the chip(20) and the frame are conjoined together face to face. A mold body(120) is then formed, and the frame and the first photoresist layer are all removed. Therefore, the metal bumps coated with the remaining copper layer(100) are protruded from the mold body(120). Finally, a solder paste is applied to each metal bump and then reflowed, so that solder balls(141) each having the inner metal bump are obtained.
申请公布号 KR20000043571(A) 申请公布日期 2000.07.15
申请号 KR19980059969 申请日期 1998.12.29
申请人 HYUNDAI ELECTRONICS IND. CO., LTD. 发明人 PARK, SANG UK;BAEK, HYEONG GIL
分类号 H01L23/50;(IPC1-7):H01L23/50 主分类号 H01L23/50
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