| 摘要 |
PURPOSE: A compression test circuit of a semiconductor device is provided to be capable of testing a plurality of bits at the same time by use of a normal data path of a semiconductor memory device. CONSTITUTION: A compression test circuit of a semiconductor device comprises a first voltage transfer part(35) connected to a first data line bus and a second voltage transfer part(36) connected to a second data line bus. The first voltage transfer part(35) consists of plural PMOS transistors(P1-P4) whose gates are connected to the first data lines(gio0-gio3), respectively. The second voltage transfer part(36) consists of plural PMOS transistors(P5-P8) whose gates are connected to the second data lines(giob0-giob3), respectively. The drains of the transistors(P1-P4) are connected to a node(N1), and the sources thereof are connected to a PMOS transistor(31) for a voltage generation. The drains of the transistors(P5-P8) are connected to a node(N2), and the sources thereof are connected to a PMOS transistor(32) for a voltage generation. The node(N1) is connected to the drain of an NMOS transistor(33) whose source is grounded, and the node(N2) is connected to the drain of an NMOS transistor(34) whose source is grounded. The transistors(31-34) are controlled in common by an inverted version of a test signal(stm_dqc). The nodes(N1,N2) are precharged through corresponding NMOS transistors(N37,N38), which are controlled in common by a mixed signal of the test signal(stm_dqc) and a precharge signal(giopcg) through a NAND gate(30).
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