| 摘要 |
PROBLEM TO BE SOLVED: To improve operation speed of a semiconductor memory having hierarchical power source structure. SOLUTION: This device is provided with a capacitor SC, connected between a sub-power source line SVL and a sub-ground line SGL, a capacitor VDC connected between a main power source line MVL and the sub-ground line SGL, and a capacity cell 102 between power sources which include a capacitor VDC connected between the sub-power source line SVL and a main ground line MGL. Thereby, the voltage drop of a sub-power source line at the time of consumption of a current of an internal circuit can be reduced, and stabilizing operation and improving operation speed of an internal circuit are performed.
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