| 摘要 |
PROBLEM TO BE SOLVED: To provide a signal processing circuit of a disk storage device facilitating synchronization between a data and a clock by detecting a phase error gradient from amplitude values sampled at discrete times even in a PR class in which the amplitude level after equalization takes 5-7 values. SOLUTION: By using a waveform value converter 101 for clipping the maximum level and minimum level with a gentle gradient of an equalized waveform among the sampled points taking 5-7 level values, and a waveform converter 102 for giving the same ideal equalized amplitude value to the ideal equalization amplitude value corresponding to this clipped waveform and a middle level with a gentle gradient, a phase error gradient is detected from the values at the present time and at the time one clock earlier to synchronize the clock phase with the data.
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