| 摘要 |
PROBLEM TO BE SOLVED: To generate a complementary internal clock signal corresponding to the timing of an external clock signal by allowing a 2nd internal clock generating circuit to detects the phase difference between 1st and 2nd external clock signals and generating a 2nd internal clock clock signal by giving it to an 1st internal clock signal. SOLUTION: The 2nd internal clock generating circuit 16 detects the phase difference between the 1st and 2nd external clock signals CLK and /CLK and a variable delay circuit 30 adds a delay quantity corresponding to the phase difference to the 1st internal clock signal CLK1 to generate the 2nd internal clock signal /CLK1. The reference clock N22 of the 1st internal clock generating circuit is supplied to a variable delay circuit 31 in the 2nd internal clock generating circuit 16. The 2nd external clock signal /CLK, on the other hand, is inputted to a 1/4 frequency divider 15 through a 2nd input buffer 14. The 1/4 frequency divider 15 supplies the inverted clock N24 of the 1/4-frequency-divided signal as a reference clock input to a phase comparator 32. |
