| 摘要 |
PROBLEM TO BE SOLVED: To provide a phase shift synchronous circuit which prevents an occupied area in a chip from being increased, also reduces power consumption and also expands a frequency range where synchronization can be taken. SOLUTION: An internal clock signal aTu whose phase is faster than that of an internal clock signal Tu is supplied to a 1st delay line DL1 through output buffer circuits 12a to 12d constituting a delay monitor DLM and also supplied to a controlling part which controls the 1st and 2nd delay lines DL1 and DL2 and is not shown in the diagram. Output buffer circuits 12e and 12f are serially connected to an output terminal of the 2nd delay line DL2. An internal clock signal Du is outputted from the circuit 12f, and an internal signal aDu whose phase is faster than that of the signal Du is outputted from the circuit 12e. |
