| 摘要 |
<p>PROBLEM TO BE SOLVED: To efficiently ensure a write-in or erase voltage by providing a first write-in level decision means deciding a write-in level of a memory cell and a second write-in level decision means which is different from the first write-in level decision means. SOLUTION: At read-out time, a P-type MOS transistor Q4 is made in a conductive state by a 'Read' signal, and P-type MOS transistors Q5, Q3 are made in a cut-off state by a PV signal and an L1 signal, and a selected memory cell current is read out as a logic level signal. In first decision level operation at a write-in operation time, the transistor Q3 is made in the conductive state by the L1 signal, and whether or not threshold of all memory cells arrive at a first decision level is decided. Then, the transistor Q5 is made to conduct with the PV signal, and the write-in decision on a second decision level is performed.</p> |
