| 摘要 |
PROBLEM TO BE SOLVED: To lessen masks in number in a manufacturing process and an integrated logic memory chip in chip size, by a method wherein an upper capacitor electrode is made to serve as a barrier layer between a second plug that extends penetration through a first dielectric layer and a second well plug of a dielectric layer on the second plug. SOLUTION: A DRAM cell is equipped with a conformal dielectric layer 12 and a flattened upper dielectric layer 13. Plugs 14 and 15 are provided so as to feed electricity to a source and a drain through the intermediary of a conformal dielectric layer 12. A trench 16 that partvially covers the plug 14 and the conformal dielectric is specified, and a conductive electrode layer 17 is formed on the exposed part of a device 1 including the wall of the trench 16, and a high-dielectric film 18 is deposited thereon. A trench 19 is formed extending to the plug 15 penetrating through the layers 18, 17, and 13. An upper capacitor electrode layer 20 and an upper plug layer 21 are formed on the surface of the device 1, and the upper electrode 20 is made to serve as a barrier layer to the plug 21. |
