DATA VARIABLE DELAY CIRCUIT

摘要

PURPOSE: A data variable delay circuit is provided to reduce an occupied area by delaying input data variably. CONSTITUTION: A data variable delay circuit comprises a control part(1), a delay part(2), and a multiplexer(3). The control part(1) counts down an external 8-bit delay value(load_value(7:0)) to generate a control signal(out_en) according to a counted value. The delay part(2) consists of 256 D-flip flops(2-1 to 2-256). A first D-flip flop(2-1) delays input data(data_in) to output the delayed data to the multiplexer(3), and each of remaining D-flip flops(2-2 to 2-256) delays an output signal of a D-flip flop of a previous stage to output the delayed signal to the multiplexer(3). The multiplexer(3) selects one of signals transferred from the delay part(2) according to the 8-bit delay value(load_value(7:0)), and outputs the selected value in response to the control signal(out_en).