| 摘要 |
PROBLEM TO BE SOLVED: To reduce a lockup time of a phase locked loop circuit. SOLUTION: A control circuit 8 resets a 1st counter 2 for a delay period of a phase of a 2nd output signal FV outputted from a 2nd counter 4 that frequency-divides an output of a voltage controlled oscillator 3 with respect to a 1st output signal FR outputted from the 1st counter 2 that frequency-divides an output of a reference signal source 1 and rests the 2nd counter 4 for a phase lead period. Thus, start of counting by the 1st and 2nd counters 2, 4 is synchronously with each other so as to match a phase difference detected by a phase comparator circuit 5 with a phase difference between the 1st and 2nd output signals FR, FV. Thus, the phase difference is properly fed back as a control voltage of the voltage controlled oscillator 3 so as to reduce a lockup time. |
