发明名称 METHOD AND DEVICE FOR IMPROVING AUTOMATIC ARRANGEMENT, RECORDING MEDIUM AND PRODUCTION OF SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a method and a device for improving automatic arrangement capable of reducing a wiring length, recording medium recording a program for executing this method and production of semiconductor device using this method. SOLUTION: After automatic arrangement, nets to pass logically equivalent signals are gathered in the same group, the terminal arrangement range of each net is found, and the area of overlapping the terminal arrangement ranges in the same group is found out. Concerning respective two nets having this overlapped area, the input terminal of the maximum wiring length between an output terminal and the input terminal in the overlapped area is found out (S30 and S31), a wiring shortening lengthΔat the time of exchanging the input terminals found out in these respective two nets is calculated (S32) and in the case ofΔ>0, processing for exchanging these two input terminals (S34) is repeated.
申请公布号 JP2000194735(A) 申请公布日期 2000.07.14
申请号 JP19980371104 申请日期 1998.12.25
申请人 FUJITSU LTD 发明人 ISHII HIDEAKI
分类号 H01L21/82;G06F17/50;(IPC1-7):G06F17/50 主分类号 H01L21/82
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