| 摘要 |
PROBLEM TO BE SOLVED: To accelerate continuous read operation and to reduce a data access time by generating first, second bit line separation signals with a bank selection signal and a sensing generation signal and generating first, second bit line pre-charge control signals with the first, second bit line separation signals. SOLUTION: A bank selection signal BKSEL is inputted to a bit line separation signal generation means 13, and the bit line separation signals BISH, BISL are enabled, and the sensing generation signal SG is inputted after it is delayed by a prescribed time, and the bit line separation signals BISH, BISL are disabled. A first line connection part 2 is turned off, and first bit lines BL1, /BL1 in a memory cell area are completely separated from sense amplifier lines SL, /SL in a sense amplifier area, and the column operation of the sense amplifier lines SL, /SL parts are performed.
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