METHODS FOR FABRICATING INTERPOLY DIELECTRICS IN NON-VOLATILE STACKED-GATE MEMORY STRUCTURES

摘要

A method of forming an improved interpoly oxide-nitride-oxide (ONO) structure in stacked gate memory cells is provided. The top oxide layer of an interpoly ONO stack is formed using Low Pressure Chemical Vapor Deposition (LPCVD) of tetraethylorthosilicate (TEOS). As a result of the relatively low processing temperatures necessary for this step, degradation of the tunnel oxide and memory cell performance associated with high thermal-budget oxide growth processes is greatly reduced. Steam densification of the TEOS layer produces a robust top oxide for the ONO dielectric, and thus, greatly reduces erosion of the top layer TEOS during subsequent processing steps (i.e., in the context of a memory array embedded in CMOS core technology). This step also tends to encourage formation of a very thin silicon oxynitride layer at the interface of the nitride and TEOS layers, thus helping to cure "pinholes" typically associated the nitride layer and further increasing the quality and reliability of the ONO structure. The improved interpoly ONO structure is found to show lower leakage current for applied electrice fields between 1 to 15MV/cm as compared to prior art.