Digitally Controlled Delay Circuit

摘要

A semiconductor integrated circuit device comprises: a first variable delay circuit having delay circuits each capable of delaying an input signal, the first variable delay circuit having a plurality of stages of delay circuits; a second variable delay circuit each having a signal delay function having a precision higher than that of the first variable delay circuit, the second variable delay circuit having a plurality of stages of delay circuits; first and second phase comparator circuits (5, 6) respectively performing comparing operations on an input clock signal and an output clock signal with respective precisions of the first and second variable delay circuits; first and second delay control circuits (3, 4) respectively controlling delay times of the first and second variable delay circuits on the basis of results of the phase comparing operations; and a number-of-stages setting circuit (11) determining a number of stages of the second variable delay circuit on the basis of a first delay time obtained when the input clock signal passes through n stages of the second variable delay circuit and a second delay time obtained when the input clock signal passes through n+1 stages thereof.