发明名称 Method and apparatus for simulating an electrical circuit design using approximate circuit element tapers
摘要 A method and apparatus for making electrical circuits having RLCG lines is disclosed. The method depicts a circuit element taper of a selected element type as dependent upon an accumulated circuit element quantity. The method matches projections of the circuit element taper with projections of an approximate taper. The approximate taper depends upon the accumulated circuit element quantity. At least one reduced quantity for circuit element quantities of the selected element type is obtained on the computer. The one reduced quantity can be arranged in a reduced RLCG line having approximately the same performance as the RLCG line. The present invention should be particularly useful in verifying timing specifications and during the making of integrated circuits.
申请公布号 US6088523(A) 申请公布日期 2000.07.11
申请号 US19960752812 申请日期 1996.11.20
申请人 CADENCE DESIGN SYSTEMS, INC. 发明人 NABORS, KEITH SHELTON;FANG, TZE-TING;WHITE, JACOB KEATON
分类号 G06F17/50;(IPC1-7):G06F15/60 主分类号 G06F17/50
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